Cell scaling is of critical importance to continued improvement of complementary metal-oxide-semiconductor (CMOS) technology. One area of increasing demand is high-density STT-MRAM. For simplicity, density is referred herein as linear density by default. If required, areal density can be computed by squaring the linear density.
A known solution to scale and, therefore, double the density of a STT-MRAM structure is to divide the magnetic tunnel junction (MTJ) pitch (P) of a two-dimensional (2D) array of MTJs in half (P/2), e.g., scaling between a 1 gigabit (1 Gb) 28 nanometer (nm) STT-MRAM and a 2 Gb 14 nm STT-MRAM, as depicted in FIGS. 1 and 2, respectively.
Referring to FIG. 1 (a cross-sectional view), a known 1 Gb (28 nm) STT-MRAM structure 100 includes a silicon (Si) substrate 101 with an active area (RX) (not shown for illustrative convenience) and an array of interconnect structures 103 and 105. In this instance, a bottom portion of each interconnect structure 103 and 105 includes a source/drain contact (CA) 107, a metal layer 109 (M1), a via 111 (V1), a metal layer 113 (M2), a via 115 (V2), and a metal layer 117 (M3). The STT-MRAM structure 100 also includes a pair of word line (WL) 119 over the Si substrate 101 between the interconnect structures 103 and 105, a transistor common 121, and a WL contact 123, e.g., W0. Further, the STT-MRAM structure 100 includes a MTJ structure 125 made up of a bottom via 127, a MTJ stack 129, and a top via 131 on each of the interconnect stacks 103 and 105, and a bit line 133 over the Si substrate 101 and on the MTJ structures 125. The P of the STT-MRAM 100 is represented by the arrow 135.
Referring to FIG. 2 (a cross-sectional view) a known 2 Gb (14 nm) STT-MRAM structure 200 includes a Si substrate 201 with an RX (not shown for illustrative convenience) and an array of interconnect structures 203, 205, 207, and 209. In this instance, a bottom portion of each interconnect structure 203, 205, 207, and 209 includes a CA 211, a metal layer 213 (M1), a via 215 (V1), a metal layer 217 (M2), a via 219 (V2), and a metal layer 221 (M3). The STT-MRAM structure 200 also includes a pair of WL 223 over the Si substrate 201 between each pair of interconnect structures, e.g., 203 and 205, a transistor common 225, and a WL contact 227, e.g., WL2, WL1, WL0. Further, the STT-MRAM structure 200 includes a MTJ structure 229 made up of a bottom via 231, a MTJ stack 233, and a top via 235 on each of the interconnect stacks 203, 205, 207, and 209, and a bit line 237 over the Si substrate 201 and on each of the MTJ structures 229. The P of the STT-MRAM structure 200 is represented by the arrow 239. However, this known solution is problematic due to the process challenges that result from dividing the P 133 of FIG. 1 in half in the STT-MRAM structure 200 such as MTJ etching leading to partial shorts; degradation in bit error rate (BER) yield; patterning complexities; dielectric gap-fill issues; inability to scale at advanced technology nodes, e.g., 7 nm; capital and tool costs; and multiple patterning costs.
A need therefore exists for methodology enabling formation of a high-density STT-MRAM without scaling the MTJ pitch or the process challenges associated with the known solution and the resulting device.